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AS4C128M32MD2A-25BIN

Name: Alliance Memory AS4C128M32MD2A-25BIN
Brand: Alliance Memory
SKU: 913-4C12832MD2A25BIN
Price: 361049 IDR
Availability: InStock

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Mouser No:

913-4C12832MD2A25BIN

Mfr. No:

AS4C128M32MD2A-25BIN

Mfr.:

Alliance Memory

Description:

DRAM LPDDR2, 4G, 128M X 32, 1.2V, 134 BALL BGA, 400MHZ, Industrial TEMP - Tray

Datasheet:

AS4C128M32MD2A-25BIN Datasheet (PDF)

ECAD Model:

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More Information

Learn more about Alliance Memory AS4C128M32MD2A-25BIN

In Stock: 66

Stock:: 66

Can Dispatch Immediately

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On Order:: 168

Expected 21/10/2026
Factory Lead Time:: 20

Weeks Estimated factory production time for quantities greater than shown.

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Minimum: 1 Multiples: 1

Unit Price:

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Ext. Price:

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Est. Tariff:

Pricing (IDR)

Qty.	Unit Price	Ext. Price
	Rp361.049	Rp361.049
	Rp334.815	Rp3.348.150
	Rp324.357	Rp8.108.925
	Rp316.469	Rp15.823.450
	Rp302.709	Rp30.270.900
	Rp295.004	Rp49.560.672
	Rp290.601	Rp146.462.904

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM Mobile - LPDDR2
Memory Size:	4 Gbit
Data Bus Width:	32 bit
Maximum Clock Frequency:	400 MHz
Package/Case:	FBGA-134
Organisation:	128 M x 32
Access Time:	5.5 ns
Supply Voltage - Min:	1.14 V
Supply Voltage - Max:	1.95 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Series:	AS4C128M32MD2A-25
Packaging:	Tray
Brand:	Alliance Memory
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	168
Subcategory:	Memory & Data Storage
Supply Current - Max:	130 mA
Unit Weight:	2,191 g

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Datasheet

AS4C128M32MD2A-25BIN Datasheet (PDF)

REACH Declaration (PDF)

Compliance Codes

CNHTS:: 8542329010
CAHTS:: 8542320020
USHTS:: 8542320036
MXHTS:: 8542320201
ECCN:: EAR99

Origin Classifications

Country of Origin:: Taiwan
Assembly Country of Origin:: Taiwan
Country of Diffusion:: Taiwan

The country is subject to change at the time of shipment.

DDR2 SDRAM

Alliance Memory DDR2 SDRAM is designed to comply with DDR2 SDRAM key features. Features such as posted CAS# with additive latency, Write latency=Read latency -1, and On-Die Termination (ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style.

Low-Power DDR2 SDRAM

Alliance Memory Low-Power DDR2 SDRAM are high-speed CMOS and dynamic-access memory internally configured as an 8-bank device. These DDR2 SDRAM feature 4-bit pre-fetch DDR architecture, programmable READ and WRITE latencies, auto Temperature Compensated Self Refresh (TCSR), and clock stop capability. The DDR2 SDRAM reduces the number of input pins in the system by using a double data rate architecture on the Command/Address (CA) bus. This CA bus transmits address, command, and bank information. These DDR2 SDRAM can achieve high-speed operation by using a double data rate architecture on the DQ (bidirectional/differential data bus) pins.