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AS4C64M4SA-7TCNTR

Name: Alliance Memory AS4C64M4SA-7TCNTR
Brand: Alliance Memory
SKU: 913-AS4C64M4SA7TCNT
Price: 111911 IDR
Availability: OutOfStock

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Mouser No:

913-AS4C64M4SA7TCNT

Mfr. No:

AS4C64M4SA-7TCNTR

Mfr.:

Alliance Memory

Description:

DRAM 256Mb, 3.3V, 143Mhz 64M x 4 SDRAM

Datasheet:

AS4C64M4SA-7TCNTR Datasheet (PDF)

ECAD Model:

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More Information

Learn more about Alliance Memory AS4C64M4SA-7TCNTR

Availability

Stock:: Non-Stocked

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Factory Lead Time:: 20 Weeks Estimated factory production time.

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Minimum: 1000 Multiples: 1000

Unit Price:

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Ext. Price:

Rp-

Est. Tariff:

Pricing (IDR)

Qty.	Unit Price	Ext. Price
Full Reel (Order in multiples of 1000)
	Rp111.911	Rp111.911.000

Alternative Packaging

Mfr. Part No.:

AS4C64M4SA-7TCN

Packaging:

Tray

Availability:

In Stock

Price:

Rp173.553

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM
Memory Size:	256 Mbit
Data Bus Width:	4 bit
Maximum Clock Frequency:	143 MHz
Package/Case:	TSOP-II-54
Organisation:	64 M x 4
Access Time:	5.4 ns
Supply Voltage - Min:	3 V
Supply Voltage - Max:	3.6 V
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 70 C
Series:	AS4C64M4SA
Packaging:	Reel
Brand:	Alliance Memory
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	1000
Subcategory:	Memory & Data Storage
Supply Current - Max:	55 mA

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Datasheet

AS4C64M4SA-7TCNTR Datasheet (PDF)

Compliance Codes

CAHTS:: 8542320020
USHTS:: 8542320024
MXHTS:: 8542320201
ECCN:: EAR99

Origin Classifications

Country of Origin:: Taiwan
Assembly Country of Origin:: Taiwan
Country of Diffusion:: Taiwan

The country is subject to change at the time of shipment.

AS4C SDRAM

Alliance Memory AS4C SDRAM is high-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.