EP3C40F780I7

Altera
989-EP3C40F780I7
EP3C40F780I7

Mfr.:

Description:
FPGA - Field Programmable Gate Array

ECAD Model:
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This product may require additional documentation to export from the United States.

In Stock: 27

Stock:
27 Can Dispatch Immediately
Factory Lead Time:
16 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
Rp-
Ext. Price:
Rp-
Est. Tariff:

Pricing (IDR)

Qty. Unit Price
Ext. Price
Rp8.247.077 Rp8.247.077

RoHS Version

Altera EP3C40F780I7N
Altera
FPGA - Field Programmable Gate Array

Product Attribute Attribute Value Select Attribute
Altera
Product Category: FPGA - Field Programmable Gate Array
Delivery Restrictions:
 This product may require additional documentation to export from the United States.
RoHS: No - RoHS Version Available
Cyclone III EP3C40
39600 LE
1.11 Mbit
535 I/O
1.15 V
1.25 V
- 40 C
+ 85 C
SMD/SMT
FBGA-780
Tray
Brand: Altera
Maximum Operating Frequency: 315 MHz
Moisture Sensitive: Yes
Number of Logic Array Blocks - LABs: 2475 LAB
Operating Supply Voltage: 1.15 V to 1.25 V
Product Type: FPGA - Field Programmable Gate Array
Factory Pack Quantity: 36
Subcategory: Programmable Logic ICs
Total Memory: 1161216 bit
Tradename: Cyclone III
Part # Aliases: 970756
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CNHTS:
8542319090
CAHTS:
8542390000
USHTS:
8542310060
JPHTS:
854239099
TARIC:
8542399000
MXHTS:
8542399901
ECCN:
3A001.a.7.a

SoC FPGA Family

Altera SoC FPGAs integrate an Arm-based hard processor system (HPS) consisting of processors, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The devices combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. These user-customizable Arm-based SoC FPGAs are ideal for reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA. They differentiate the end product with custom hardware and software and add support for virtually any interface standard or protocol in the FPGA.