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GS8162Z36DB-200M

Name: GSI Technology GS8162Z36DB-200M
Brand: GSI Technology
SKU: 464-GS8162Z36DB-200M
Price: 1740485 IDR
Availability: OutOfStock

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Mouser No:

464-GS8162Z36DB-200M

Mfr. No:

GS8162Z36DB-200M

Mfr.:

GSI Technology

Description:

SRAM 2.5 or 3.3V 512K x 36 18M

Datasheet:

GS8162Z36DB-200M Datasheet (PDF)

ECAD Model:

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More Information

Learn more about GSI Technology GS8162Z36DB-200M

Shipping Alert:

This product may require additional documentation to export from the United States.

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Ext. Price:

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Pricing (IDR)

Qty.	Unit Price	Ext. Price
	Rp1.740.485	Rp36.550.185
	Rp1.633.528	Rp68.608.176
	Rp1.587.663	Rp166.704.615
252	Quote

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	GSI Technology
Product Category:	SRAM
Delivery Restrictions:	This product may require additional documentation to export from the United States.
Memory Size:	18 Mbit
Organisation:	512 k x 36
Access Time:	6.5 ns
Maximum Clock Frequency:	200 MHz
Interface Type:	Parallel
Supply Voltage - Max:	3.6 V
Supply Voltage - Min:	2.3 V
Supply Current - Max:	255 mA, 260 mA
Minimum Operating Temperature:	- 55 C
Maximum Operating Temperature:	+ 125 C
Mounting Style:	SMD/SMT
Package/Case:	BGA-119
Packaging:	Tray
Brand:	GSI Technology
Memory Type:	SDR
Moisture Sensitive:	Yes
Product Type:	SRAM
Series:	GS8162Z36DB
Factory Pack Quantity:	21
Subcategory:	Memory & Data Storage
Tradename:	NBT SRAM
Type:	NBT Pipeline/Flow Through

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Datasheet

GS8162Z36DB-200M Datasheet (PDF)

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Compliance Codes

CNHTS:: 8542319090
CAHTS:: 8542320041
USHTS:: 8542320041
JPHTS:: 854232029
KRHTS:: 8542321020
TARIC:: 8542324500
MXHTS:: 8542320201
ECCN:: 3A001.a.2.c

Origin Classifications

Country of Origin:: Not available
Assembly Country of Origin:: Not available
Country of Diffusion:: Not available

The country is subject to change at the time of shipment.

NBT SRAMs

GSI Technology NBT SRAMs are 144Mbit and 288Mbit Synchronous Static SRAMs that utilize all available bus bandwidth. The SRAMs achieve this by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. The devices' simplified interface is designed to use a data bus's maximum bandwidth. Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock.