IS43R16320D-6TLI

ISSI
870-IS43R16320D-6TLI
IS43R16320D-6TLI

Mfr.:

Description:
DRAM 512M (32Mx16) 166MHz 2.5v DDR SDRAM

ECAD Model:
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In Stock: 280

Stock:
280 Can Dispatch Immediately
Factory Lead Time:
8 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1   Maximum: 89
Unit Price:
Rp-
Ext. Price:
Rp-
Est. Tariff:

Pricing (IDR)

Qty. Unit Price
Ext. Price
Rp191.349 Rp191.349
Rp177.773 Rp1.777.730
Rp172.452 Rp4.311.300
Rp168.233 Rp8.411.650

Possible Replacement

ISSI IS43R16320F-6TLI
ISSI
DRAM 512M 32Mx16 166MHz DDR 2.5V

Product Attribute Attribute Value Select Attribute
ISSI
Product Category: DRAM
RoHS:  
SDRAM - DDR
512 Mbit
16 bit
166 MHz
TSOP-II-66
32 M x 16
6 ns
2.3 V
2.7 V
- 40 C
+ 85 C
IS43R16320D
Tray
Brand: ISSI
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 108
Subcategory: Memory & Data Storage
Supply Current - Max: 370 mA
Unit Weight: 2,188 g
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CNHTS:
8542329000
USHTS:
8542320028
JPHTS:
8542320216
KRHTS:
8542321010
MXHTS:
8542320299
ECCN:
EAR99

DDR SDRAM

ISSI 512-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages. The device is available in 8-bit, 16-bit, and 32-bit data word sizes. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. ISSI 512-Mbit DDR SDRAM commands are registered on the positive edges of CLK.

IS43R32800D 8Mx32 256-Mbit DDR SDRAM

ISSI IS43R32800D 8Mx32 256-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64MB to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages.