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AD3421QRWERQ1

Name: Texas Instruments AD3421QRWERQ1
Brand: Texas Instruments
SKU: 595-AD3421QRWERQ1
Price: 523228 IDR
Availability: OutOfStock

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Mouser No:

595-AD3421QRWERQ1

Mfr. No:

AD3421QRWERQ1

Mfr.:

Texas Instruments

Description:

Analog to Digital Converters - ADC Automotive quad-chan nel 12-bit 25-MSPS A 595-AD3421QRWETQ1

Datasheet:

AD3421QRWERQ1 Datasheet

ECAD Model:

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More Information

Learn more about Texas Instruments AD3421QRWERQ1

Availability

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Factory Lead Time:: 18 Weeks Estimated factory production time.

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Minimum: 2000 Multiples: 2000

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Pricing (IDR)

Qty.	Unit Price	Ext. Price
Full Reel (Order in multiples of 2000)
	Rp523.228	Rp1.046.456.000

Alternative Packaging

Mfr. Part No.:

AD3421QRWETQ1

Packaging:

Reel, Cut Tape, MouseReel

Availability:

In Stock

Price:

Rp832.541

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Similar Product

Mfr.:

Texas Instruments

Mfr. No:

AD3421QRWETQ1

Description:

Analog to Digital Converters - ADC Automotive quad-chan nel 12-bit 25-MSPS A 595-AD3421QRWERQ1

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Analog to Digital Converters - ADC
RoHS:
Series:	ADC3421
Mounting Style:	SMD/SMT
Package/Case:	VQFNP-56
Resolution:	12 bit
Number of Channels:	4 Channel
Interface Type:	Serial
Sampling Rate:	25 MS/s
Input Type:	Differential
Architecture:	Pipeline
Analogue Supply Voltage:	1.8 V
Digital Supply Voltage:	1.8 V
SNR - Signal to Noise Ratio:	68.9 dB
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 125 C
Packaging:	Reel
Brand:	Texas Instruments
ENOB - Effective Number of Bits:	11.1 bit
Gain Error:	- 2 %/FSR
Moisture Sensitive:	Yes
Number of Converters:	4 Converter
Output Type:	Digital
Power Consumption:	177 mW
Product:	Analog to Digital Converters
Product Type:	ADCs - Analog to Digital Converters
Reference Type:	Internal
SFDR - Spurious Free Dynamic Range:	82 dBc
Shutdown:	No Shutdown
SINAD - Signal to Noise and Distortion Ratio:	68.7 dB
Factory Pack Quantity:	2000
Subcategory:	Data Converter ICs
THD - Total Harmonic Distortion:	80 dBc
Type:	Automotive

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Compliance Codes

USHTS:: 8542390030
ECCN:: EAR99

Origin Classifications

Country of Origin:: Not available
Assembly Country of Origin:: Not available
Country of Diffusion:: Not available

The country is subject to change at the time of shipment.

ADC342x/ADC342x-Q1 Quad-Channel 12-Bit ADCs

Texas Instruments ADC342x/ADC342x-Q1 Quad-Channel 12-Bit Analog-to-Digital Converters are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converters (ADCs). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. The ADC342x-Q1 devices are AEC-Q100 qualified for automotive applications.

ADC3x High-Speed 12/14-Bit ADCs

Texas Instrument ADC3x High-Speed 12/14-Bit Analog-to Digital Converters are a high-linearity, ultra-low power, dual-channel, 12 or 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converters (ADCs). These devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC3x supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12 or 14-bit output data from each channel.
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