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LMK5C22212ARGCRS1

Name: Texas Instruments LMK5C22212ARGCRS1
Brand: Texas Instruments
SKU: 595-LMK5C22212ARGCRS
Price: 667427 IDR
Availability: OutOfStock

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Mouser No:

595-LMK5C22212ARGCRS

Mfr. No:

LMK5C22212ARGCRS1

Mfr.:

Texas Instruments

Description:

Clock Synthesizer/Jitter Cleaner Three DPLL two APLL two-input 12-outp

Lifecycle:

New Product:

New from this manufacturer.

Datasheet:

LMK5C22212ARGCRS1 Datasheet

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Learn more about Texas Instruments LMK5C22212ARGCRS1

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Stock:: Non-Stocked

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Factory Lead Time:: 18 Weeks Estimated factory production time.

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Minimum: 2500 Multiples: 2500

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Ext. Price:

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Pricing (IDR)

Qty.	Unit Price	Ext. Price
Full Reel (Order in multiples of 2500)
	Rp667.427	Rp1.668.567.500

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Clock Synthesizer/Jitter Cleaner
Number of Outputs:	12 Output
Max Output Freq:	1.25 GHz
Output Level:	CML, LVCMOS, LVDS, LVPECL
Input Level:	HCSL, LVCMOS, LVDS, LVPECL, XTAL
Package/Case:	VQFN-64
Maximum Input Frequency:	800 MHz
Supply Voltage - Min:	3.135 V
Supply Voltage - Max:	3.465 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Series:	LMK5C22212AS1
Mounting Style:	SMD/SMT
Packaging:	Reel
Brand:	Texas Instruments
Development Kit:	LMK5B12212EVM
Moisture Sensitive:	Yes
Operating Supply Current:	890 mA
Product:	Network Synchronizers
Product Type:	Clock Synthesizers / Jitter Cleaners
Factory Pack Quantity:	2500
Subcategory:	Clock & Timer ICs

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Datasheet

LMK5C22212ARGCRS1 Datasheet

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USHTS:: 8542390090
MXHTS:: 8542399999
ECCN:: EAR99

LMK5C22212AS1 Network Synchronizer

Texas Instruments LMK5C22212AS1 Network Synchronizer is a high-performance jitter cleaner and network synchronizer designed to meet the stringent requirements of wireless communications and infrastructure applications. The device is bundled with software support for IEEE-1588 PTP synchronization to a primary reference clock source. The network synchronizer integrates two DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.