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LMK5C33216ARGCR

Name: Texas Instruments LMK5C33216ARGCR
Brand: Texas Instruments
SKU: 595-LMK5C33216ARGCR
Price: 458650 IDR
Availability: OutOfStock

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Mouser No:

595-LMK5C33216ARGCR

Mfr. No:

LMK5C33216ARGCR

Mfr.:

Texas Instruments

Description:

Clock Synthesizer/Jitter Cleaner Three DPLL three AP LL two-input and 16

Datasheet:

LMK5C33216ARGCR Datasheet

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This product may require additional documentation to export from the United States.

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Factory Lead Time:: 18 Weeks Estimated factory production time.

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Minimum: 2500 Multiples: 2500

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Ext. Price:

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Pricing (IDR)

Qty.	Unit Price	Ext. Price
	Rp458.650	Rp1.146.625.000

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Clock Synthesizer/Jitter Cleaner
Delivery Restrictions:	This product may require additional documentation to export from the United States.
RoHS:
Number of Outputs:	16 Output
Max Output Freq:	1.25 GHz
Output Level:	CML, HSCL, LVCMOS, LVDS, LVPECL
Input Level:	Differential, Single-Ended
Package/Case:	VQFN-64
Maximum Input Frequency:	200 MHz, 800 MHz
Supply Voltage - Min:	3.135 V
Supply Voltage - Max:	3.465 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 105 C
Series:	LMK5C33216A
Mounting Style:	SMD/SMT
Brand:	Texas Instruments
Moisture Sensitive:	Yes
Operating Supply Current:	950 mA, 1.09 A, 1.205 A
Product:	Synchronizers / Jitter Cleaners
Product Type:	Clock Synthesizers / Jitter Cleaners
Factory Pack Quantity:	2500
Subcategory:	Clock & Timer ICs
Type:	High-Performance Network Synchronizer and Jitter Cleaner

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Datasheet

LMK5C33216ARGCR Datasheet

PCN

Product Change Notification 2025-3-28 (PDF)

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USHTS:: 8542390090
MXHTS:: 8542399999
ECCN:: 3A001.A.2.A

LMK5C33216A High-Performance Network Synchronizer

Texas Instruments LMK5C33216A High-Performance Network Synchronizer includes a jitter cleaner designed to meet stringent wireless communications and infrastructure application requirements. The network synchronizer integrates three DPLLs to provide hitless jitter and switching attenuation with programmable loop bandwidth and no external loop filters. This feature maximizes the flexibility and ease of use of the device. Each DPLL phase locks a paired APLL to a reference input.