SN74AC2G101PWR

Texas Instruments
595-SN74AC2G101PWR
SN74AC2G101PWR

Mfr.:

Description:
Flip-Flops Two-channel configur able gate for clock

Lifecycle:
New Product:
New from this manufacturer.
ECAD Model:
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In Stock: 3.000

Stock:
3.000 Can Dispatch Immediately
Factory Lead Time:
18 Weeks Estimated factory production time for quantities greater than shown.
Long lead time reported on this product.
Minimum: 1   Multiples: 1
Unit Price:
Rp-
Ext. Price:
Rp-
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 3000)

Pricing (IDR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™
Rp10.274 Rp10.274
Rp7.173 Rp71.730
Rp6.439 Rp160.975
Rp5.596 Rp559.600
Rp5.210 Rp1.302.500
Rp4.972 Rp2.486.000
Rp4.843 Rp4.843.000
Full Reel (Order in multiples of 3000)
Rp4.513 Rp13.539.000
Rp4.385 Rp26.310.000
† A MouseReel™ fee of Rp98.000 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable.

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Flip-Flops
RoHS:  
D-Type
2 Circuit
Push-Pull
TSSOP-16
Schmitt-Trigger
Non-Inverting
11.3 ns
- 24 mA
24 mA
1.5 V
6 V
SMD/SMT
- 40 C
+ 125 C
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Maximum Clock Frequency: 175 MHz
Number of Input Lines: 6 Line
Number of Output Lines: 1 Line
Product Type: Flip Flops
Series: SN74AC2G101
Factory Pack Quantity: 3000
Subcategory: Logic ICs
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Compliance Codes
USHTS:
8542390090
TARIC:
8542319000
MXHTS:
8542399999
ECCN:
EAR99
Origin Classifications
Country of Origin:
Malaysia
Assembly Country of Origin:
Malaysia
Country of Diffusion:
United States
The country is subject to change at the time of shipment.

SN74AC2G101/SN74AC2G101-Q1 Gates

Texas Instruments SN74AC2G101/SN74AC2G101-Q1 Gates feature two independent D-type flip-flops with rising-edge triggered configurable logic clock, active-low clear, and data inputs. The clock inputs can be arranged for multiple 1- and 2-input logic functions, including buffer, inverter, AND, OR, NAND, NOR, XOR, and XNOR. All inputs have a Schmitt-trigger architecture to support slow or noisy input signals.