SN74HC393DR

Texas Instruments
595-SN74HC393DR
SN74HC393DR

Mfr.:

Description:
Counter ICs Dual 4-Bit Binary Co unters A 595-SN74HC A 595-SN74HC393D

ECAD Model:
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In Stock: 8.417

Stock:
8.417 Can Dispatch Immediately
Factory Lead Time:
6 Weeks Estimated factory production time for quantities greater than shown.
Long lead time reported on this product.
Minimum: 1   Multiples: 1
Unit Price:
Rp-
Ext. Price:
Rp-
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 2500)

Pricing (IDR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™
Rp9.356 Rp9.356
Rp6.531 Rp65.310
Rp5.852 Rp146.300
Rp5.082 Rp508.200
Rp4.660 Rp1.165.000
Rp4.495 Rp2.247.500
Rp4.366 Rp4.366.000
Full Reel (Order in multiples of 2500)
Rp4.110 Rp10.275.000
Rp3.999 Rp19.995.000
† A MouseReel™ fee of Rp98.000 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable.

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Counter ICs
RoHS:  
SMD/SMT
SOIC-14
Binary
HC
4 bit
Up
2 V to 6 V
- 40 C
+ 85 C
SN74HC393
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Product Type: Counter ICs
Factory Pack Quantity: 2500
Subcategory: Counter ICs
Unit Weight: 122,400 mg
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Compliance Codes
CNHTS:
8542399000
CAHTS:
8542390000
USHTS:
8542390090
JPHTS:
8542390990
TARIC:
8542319000
MXHTS:
8542399999
ECCN:
EAR99
Origin Classifications
Country of Origin:
Malaysia
Assembly Country of Origin:
Malaysia
Country of Diffusion:
United States
The country is subject to change at the time of shipment.

SN74HC393/SN74HCS393 Dual 4-Bit Binary Counters

Texas Instruments SN74HC393/SN74HCS393 Dual 4-Bit Binary Counters contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK) input. N-bit binary counters can be implemented with each package, providing the capability of dividing by 256. The Texas Instruments SN74HC393/SN74HCS393 have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.