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SN74LV2T74PWREP

Name: Texas Instruments SN74LV2T74PWREP
Brand: Texas Instruments
SKU: 595-SN74LV2T74PWREP
Price: 47700 IDR
Availability: InStock

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Mouser No:

595-SN74LV2T74PWREP

Mfr. No:

SN74LV2T74PWREP

Mfr.:

Texas Instruments

Description:

Flip-Flops BD9 SPIN EP SN74LV2T 74PWREP

Datasheet:

SN74LV2T74PWREP Datasheet

ECAD Model:

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More Information

Learn more about Texas Instruments SN74LV2T74PWREP

In Stock: 2.560

Stock:: 2.560 Can Dispatch Immediately

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Factory Lead Time:: 12 Weeks Estimated factory production time for quantities greater than shown.

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Pricing (IDR)

Qty.	Unit Price	Ext. Price
	Rp47.700	Rp47.700
	Rp35.591	Rp355.910
	Rp32.656	Rp816.400
	Rp29.170	Rp2.917.000
	Rp27.702	Rp6.925.500
	Rp26.602	Rp13.301.000
	Rp25.868	Rp25.868.000
	Rp24.767	Rp74.301.000
	Rp24.217	Rp145.302.000

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Flip-Flops
RoHS:
Logic Family:	LV
Number of Circuits:	2 Circuit
Output Type:	Push-Pull
Package/Case:	TSSOP-14
Input Type:	CMOS
High Level Output Current:	- 8 mA
Low Level Output Current:	8 mA
Supply Voltage - Min:	1.8 V
Supply Voltage - Max:	5.5 V
Mounting Style:	SMD/SMT
Minimum Operating Temperature:	- 55 C
Maximum Operating Temperature:	+ 125 C
Brand:	Texas Instruments
Maximum Clock Frequency:	66.2 MHz
Number of Input Lines:	8 Input
Number of Output Lines:	4 Output
Product Type:	Flip Flops
Series:	SN74LV2T74
Factory Pack Quantity:	3000
Subcategory:	Logic ICs

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Datasheet

SN74LV2T74PWREP Datasheet

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Compliance Codes

CAHTS:: 8542390000
USHTS:: 8542390090
TARIC:: 8542319000
MXHTS:: 8542399999
ECCN:: EAR99

Origin Classifications

Country of Origin:: Malaysia
Assembly Country of Origin:: Not available
Country of Diffusion:: Not available

The country is subject to change at the time of shipment.

SN74LV2T74/SN74LV2T74-Q1 Dual D-Type Flip-Flop

Texas Instruments SN74LV2T74/SN74LV2T74-Q1 Dual D-Type Flip-Flops contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V_CC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.