D12.31492S.001

Apacer
908-D12.31492S.001
D12.31492S.001

Mfr.:

Description:
Memory Modules DDR5 DIMM 4800 8GB JEDEC 1.0 version

Datasheet:
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In Stock: 9

Stock:
9 Can Dispatch Immediately
Factory Lead Time:
4 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
Rp-
Ext. Price:
Rp-
Est. Tariff:

Pricing (IDR)

Qty. Unit Price
Ext. Price
Rp11.582.564 Rp11.582.564
Rp10.645.083 Rp106.450.830

Product Attribute Attribute Value Select Attribute
Apacer
Product Category: Memory Modules
RoHS:  
UDIMMs
8 GB
SDRAM - DDR5
4800 Mb/s
1.067 V to 1.166 V
+ 85 C
288 Pin
Brand: Apacer
Minimum Operating Temperature: 0 C
Packaging: Bulk
Product Type: Memory Modules
Factory Pack Quantity: 1
Subcategory: Memory & Data Storage
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Attributes selected: 0

Datasheet

CAHTS:
8473302000
USHTS:
8473301140
MXHTS:
8473300401
ECCN:
EAR99

8GB DDR5 SDRAM DIMMs

Apacer Technology Inc. 8GB DDR5 SDRAM DIMMs are 4800Mbps, 16-bit prefetch architecture, and dual in-line memory modules. These memory modules consist of 4 pieces of 1G x 16bits DDR5 synchronous DRAMs (SDRAM) in FBGA packages and 8K Bits EEPROM.  The DDR5 DIMMs support 32 internal banks (x8, x4), 16 internal banks (x16), and an On-DIMM thermal sensor. These DDR5 memory modules operate within a supply voltage range of 1.067V to 1.166V and a temperature range (Tcase) of 0°C to 85°C. The DDR5 memory modules are RoHS compliant, JEDEC standard compliant, sPPR capability, and hPPR capability. The 8GB DDR5 SDRAM DIMMs are available in two variations a D22.31491S.001 (SO-DIMM) with 262 pins and D12.31492S.001 (UDIMM) with 288 pins. 

Embedded Memory Modules DDR5 UDIMM

Apacer Technology Inc. Embedded Memory Modules DDR5 UDIMM utilize original high-quality DRAM ICs and feature memory transfer rates of up to 5600MHz. The devices integrate an on-die ECC mechanism that significantly strengthens the reliability, availability, and serviceability of the DRAM IC. Furthermore, the Apacer DDR5 modules include a power management IC (PMIC) on the module to control the system’s load while improving signal integrity and compatibility.

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