Back to Alliance Memory

Alliance Memory P33 Micron Parallel NOR Flash Embedded Memory

Alliance Memory P33 Micron Parallel NOR Flash Embedded Memory devices offer more density in less space, high-speed interface device, and support for code and data storage. These memory devices feature high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices. The P33 flash memory devices are manufactured using Micron 65nm process technology and provide high performance at low voltage on a 16-bit data bus. These memory devices default to asynchronous page-mode read upon initial power-up or return from reset and configuring the read configuration register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal.

The P33 memory devices incorporate technology that enables fast factory PROGRAM and ERASE operations. These memory devices support READ operations with VCC at the low voltages and ERASE and PROGRAM operations with VPP at the low voltages or VPPH. The P33 memory devices consist of industry-standard command sequence that invokes program and erase automation. Each ERASE operation erases one block. These memory devices include enhanced protection via password access that supports write and/or read access protection of user-defined blocks. The P33 memory devices also provide the full-device OTP security feature.

Features

  • High performance
  • Easy BGA package features:
    • 95ns initial access for 512Mb, 1Gb Easy BGA
    • 100ns initial access for 2Gb Easy BGA
    • 25ns 16-word asychronous page read mode
    • 52MHz (Easy BGA) with zero WAIT states and 17ns clock-to-data output synchronous burst read mode
    • 4-, 8-, 16-, and continuous word options for burst mode
  • TSOP package features:
    • 105ns initial access for 512Mb, 1Gb TSOP
  • Both Easy BGA and TSOP package features:
    • Buffered Enhanced Factory Programming (BEFP) at 2MB/s (TYP) using a 512-word buffer
    • 3V buffered programming at 1.46MB/s (TYP) using a 512-word buffer
  • Architecture:
    • Highest density MLC at lowest cost
    • Symmetrically blocked architecture (512Mb, 1Gb, 2Gb)
    • Asymmetrically blocked architecture (512Mb, 1Gb); four 32KB parameter blocks: top or bottom configuration
    • 128KB main blocks
    • Blank check to verify an erased block
  • Security:
    • One-Time Programmable register:
      • 64 OTP bits programmed with unique information from Micron and 2112 OTP bits available for customer programming
    • VPP = VSS absolute write protection
    • Power-transition erase/program lockout
    • Individual zero-latency block locking
    • Individual block lock-down
    • Password access
  • Bottom boot block configuration
  • Software:
    • 25μs (typical) program suspend
    • 25μs (typical) erase suspend
    • Flash Data Integrator optimized
    • Basic command set and Extended Function Interface (EFI) command set compatible
    • Common flash interface
  • Density and packaging:
    • 56-lead TSOP package (512Mb, 1Gb)
    • 64-ball Easy BGA package (512Mb, 1Gb, 2Gb)
    • 16-bit wide data bus

Specifications

  • Voltage and power:
    • 2.3V to 3.6V VCC (core)
    • 2.3V to 3.6V VCCQ (I/O) voltage
    • 70µA (typical) for 512Mb; 75µA (typical) for 1Gb standby current
    • 21mA (typical), 24mA (maximum) continuous synchronous read current @ 52MHz
  • Quality and reliability:
    • JESD47 compliant
    • -40°C to 85°C operating temperature range
    • Minimum 100,000 ERASE cycles per block
    • 65nm process technology

Easy BGA Block Diagram

Block Diagram - Alliance Memory P33 Micron Parallel NOR Flash Embedded Memory
Published: 2020-12-09 | Updated: 2022-03-11