NXP Semiconductors PCAL6534 34-bit General Purpose I/O Expander
NXP Semiconductors PCAL6534 34-bit General Purpose I/O (GPIO) Expander provides remote I/O expansion for most microcontroller families via the Fast-mode Plus (Fm+) I2C-bus interface. The PCAL6534 fully meets the Fm+ I2C-bus specification at speeds to 1MHz. This device also implements Agile I/O, which is an additional feature set specifically designed to enhance I/O interface. These additional features include programmable output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, and programmable open-drain or push-pull outputs. The ultra-low-voltage interface of the PCAL6534 allows for direct connection to microcontrollers operating down to 0.8V.The NXP Semiconductors PCAL6534 includes level translating from the 1.65V to 5.5V I/O range, Agile I/O input latch, programmable output current, and integrated resistors. The PCAL6534 features a wide voltage range, enabling it to match ultra-low voltage FPGAs and processors. The PCAL6534 can also simplify routing by pulling the I/Os for system management way from the processor, which may be densely packed with other critical functions.
The PCAL6534 is offered in a compact, 48-bump VFBGA (Very Thin Profile Fine Pitch Ball Grid Array) package, with 0.4mm bump spacing.
Features
- Operating power supply voltage range of 0.8V to 3.6V on the I2C-bus
- Allows bidirectional voltage-level translation and GPIO expansion between 0.8V to 3.6V SCL/SDA and 1.8V, 2.5V, 3.3V, 5.5V I/O ports
- Low standby current consumption: 2.0µA typical at 3.3V VDD(P)
- Schmitt trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs
- Vhys = 0.05V (typical) at 0.8V
- Vhys = 0.18V (typical) at 1.8V
- Vhys = 0.33V (typical) at 3.3V
- 5.5V tolerant I/O ports and 3.6V tolerant I2C-bus lines
- 1MHz Fast-mode Plus I2C-bus
- Active LOW reset input (RESET)
- Open-drain active LOW interrupt output (INT)
- Internal power-on reset
- Noise filter on SCL/SDA inputs
- Latched outputs with 25mA drive maximum capability for directly driving LEDs
- Latch-up performance exceeds 100mA per JESD 78, Class II
- 2.6mm x 3.0mm package dimensions
- 0.4mm bump spacing
- ESD protection exceeds JESD
- 222000V Human-Body Model (A114-A)
- 1000 V Charged-Device Model (C101)Package type: VFBGA-42
- Agile I/O Features
- Output port configuration
- Bank selectable or pin selectable push-pull or open-drain output stages
- Interrupt status
- Read-only register identifies the source of an interrupt
- Bit-wise I/O programming features
- Output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance applications
- Input latch: Input Port register values changes are kept until the Input Port register is read
- Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable
- Pull-up/pull-down selection: 100 kΩ pull-up/pull-down resistor selection
- Interrupt mask: mask prevents the generation of the interrupt when input changes state to prevent spurious interrupts
- Interrupt edge specification on a bit-by-bit basis
- Interrupt individual clear without disturbing other events
- Read all interrupt events without clear
- Switch debounce hardware
- General call software reset
- I2C software Device ID function
- Output port configuration
Applications
- Automotive
- Automotive window control
- Consumer Electronics
- Consumer phones and game controllers
- Networking
- Networking switches and routers
- Power and Energy
- IO buttons
Block Diagram
Typical Application Circuit
Videos
Additional Resources
Published: 2019-03-27
| Updated: 2023-07-06
